Document Type : Original Manuscript
Authors
1 Faculty of Marine Engineering, Khorramshahr University of Marine Science and Technology, Khorramshahr, Iran.
2 Department of Basic Sciences, Abadan Faculty of Petroleum Engineering, Petroleum University of Technology, Abadan, Iran
3 دانشکده مهندسی دریا - گروه الکترونیک و مخابرات دریایی
Abstract
The residue number system has a parallel computational structure with carry-free operations and is widely used in cases such as digital signal processing, cryptography, design of FIR filters, etc. In this paper we design an efficient reverse converter for the four-moduli set {〖2^(n-2)+1,2〗^(n-3)-1,2^(n-3)+1,2^(n-5)-1}. In this moduli set, due to the selection of well-formed and balanced modulus, it leads to optimal hardware implementation, with minimum area utilization and minimum time delay. The main advantage of this design is the use of a ROM free and adder base hardware structure. The proposed moduli set are relatively prime to most existed moduli sets in literature and as results it can be employed in the implementation of Montgomery multiplication. The proposed reverse converter has a two-level structure. In the first level, the Chinese remainder theorem is used, and in the second level, the Mixed-radix conversion is used to calculate the final weighted number. The results of computational theory show low time latency and minimal hardware space in this design.
Keywords
- : Residue Number System (RNS)
- Chinese Remainder Theorem (CRT)
- Mixed-Radix Conversion (MRC)
- Reverse Converters
Main Subjects
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